Dear Dr. Gui:

It is our pleasure to accept your manuscript entitled "A 12-bit 20-kS/s 640-nW SAR ADC with a VCDL-Based Open-Loop Time-Domain Comparator" for publication in the IEEE Transactions on Circuits and Systems II: Express Briefs.  

课题组近期完成的纳瓦级超低功耗SAR ADC芯片设计研究成果发表在IEEE电路与系统领域顶刊IEEE TCAS-II上。该工作实现了精度为12bit，采样率为20~200kS/s的SAR ADC，最低功耗仅为640纳瓦。课题组在该芯片设计中提出和采用了一系列低噪声和超低功耗设计技术，在0.18-um 标准CMOS工艺下实现了和同类芯片相比更低的功耗。

Abstract—This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise and ultra-low power performance. By employing the mixed switching scheme, the segmented capacitive digital-to-analog converter (CDAC) arrays as well as the synchronous data-weighted averaging (DWA) calibration block, the proposed SAR ADC can operate from 1.8 V down to 0.8 V at 20-200 kS/s. The designed ADC is fabricated in a 0.18-um CMOS process and the measurement results show the proposed SAR ADC achieves an SNDR of 65-dB with power consumption of 647 nW from a 0.8 V power supply at 20 kS/s.