发布时间：2016-09-12

文章标题：First Tape-Out in CWRU

内容：

 As an undergraduate student in Case Western Reserve University, Professor Shiquan Fan advices me on the energy harvesting project. The overall goal of this project is to acquire vibrational energy from the environment in order to generate DC voltage that can be used for various applications. In this project, we have designed power manage IC for piezoelectric energy harvesting systems. Our design mainly consists of 5 parts: (1) active rectifier, (2) Buck-Boost DC-to-DC converter, (3) LDO, (4) fast start-up current reference circuit, and (5) full-integrated low power temperature sensor.

The first part of my IC design is active rectifier that converts AC input from Piezoelectric transducer into DC voltage for the rest of analog systems. DC-DC Buck-Boost converter is also implemented in my chip design in order to transfer the energy obtained from Piezoelectric transducer more efficiently on to the storage capacitor with a fixed voltage. In addition, all the DC bias current will be generated from fast startup current reference circuit with relatively short startup time. The final part of my IC design is the 500nW low power temperature sensor. Vibrational energy obtained by the energy harvesting system will be used to provide DC voltage supply for this on-chip temperature sensor.

We designed the power manage IC chip in 0.5 µm CMOS process with three metal layers and 2 poly layers ON-SEMI. Since we only have one and a half month to design schematics and layouts, we have extremely limited time to achieve 5 parts in one 1.5mm x 1.5mm power manage IC for piezoelectric energy harvesting systems. In order to complete the work on time, professor Shiquan Fan gives me tons of help on schematic design of fast startup current reference circuit and low power temperature sensor. One important thing that I learned is the trade-off when I decide to proper dimensions of transistors during schematic design. In addition, professor Shiquan Fan advise me on layout designs of the whole chip. More specifically, he teaches me how to efficiently save more chip area during the layout without violation Deign Rules. Finally, we successfully sent our layout information to MOSIS and ideally we can get our chip back on October 4^th.

Liuming Zhao

09/12/2016